stream2roce
Turns an AXI4-Stream into RoCEv2 RDMA writes entirely in FPGA logic. Streams sensor data straight into remote host memory, from 1 GbE without transceivers up to 800 Gbit/s.
Every core ships as portable VHDL, with state-of-the-art verification and precise documentation.
Technology-independent RTL, with a focus on portability across every major FPGA vendor.
Our IP cores come from the same engineering discipline as our design services: clean, portable VHDL with minimal vendor dependencies, verified with modern frameworks such as UVVM and VUnit. Our IP cores are designed and tested for Efinix, Lattice, AMD/Xilinx, Altera and Microchip, and are in continuous use across dozens of industrial projects.
We deliver first-class service: free bug-fix support for the core over several years, integration support and optional customization and porting engagements.
Available for the FPGA families of Efinix, Lattice, AMD/Xilinx, Altera and Microchip.
Turns an AXI4-Stream into RoCEv2 RDMA writes entirely in FPGA logic. Streams sensor data straight into remote host memory, from 1 GbE without transceivers up to 800 Gbit/s.
SPI Slave core connecting low-cost FPGAs to microcontrollers, SoCs or other FPGAs. A patented sync scheme lets the SPI clock exceed the FPGA system clock — high SPI rates even on small FPGAs.
SPI Master core for high-performance SPI communication with microcontrollers, SoCs and other FPGAs. Flexible configuration supporting all SPI modes for broad device compatibility.
High-throughput FFT core with a parallel streaming architecture that processes multiple samples per clock cycle — far beyond single-sample-per-cycle FFT cores.
Cost-effective PCB version detection using a single FPGA pin. Precise version detection, minimal I/O, easy integration on any FPGA, scalable to many board revisions.
USB 2.0 device controller with a ULPI interface (LS/FS/HS). Each endpoint is exposed as an AXI-Stream — no CPU-RAM round-trip. Up to 350 Mbit/s bulk IN measured.
Didn't find the IP you need? Tell us your requirements and we'll scope a tailored core from our design services.
A complete, integration-ready package, including documentation, verification and an example project.
Tell us your interface, target FPGA and performance goal. We take the right core off the shelf, or build a tailored one for you.
Get in touch