Massively scalable
Multiple parallel SWI3S buses, up to 12 microphones per bus — demonstrated in-house with up to 144 microphones.
Resource-efficient FPGA IP for the MIPI SoundWire I3S (SWI3S) audio interface — scaling from a handful of microphones to 144 and beyond.
P2L2 develops highly resource-efficient FPGA IP for digital MEMS microphone arrays. Our SWI3S manager IP connects large numbers of digital microphones to an FPGA host with a minimal logic footprint and scales cleanly across multiple parallel buses to support arbitrary channel counts.
Vendor-neutral RTL, adaptable to your target FPGA and channel count.
Engineered to connect many digital MEMS microphones to a single FPGA while leaving as much of the device as possible for your own processing.
Multiple parallel SWI3S buses, up to 12 microphones per bus — demonstrated in-house with up to 144 microphones.
Designed for a small FPGA footprint, leaving headroom for your own signal processing.
Vendor-neutral RTL, adaptable to your target device and channel count.
Proven in a real customer project for a high-channel-count audio application.
Designed for the MIPI SoundWire I3S (SWI3S) audio interface.
SWI3S is a two-wire digital audio interface that carries the streams of several microphones on a single bus. Our IP implements the manager (host) side of that interface on your FPGA and instantiates as many parallel buses as your channel count requires, so a single device can gather a large, coherent microphone array. The figures on this page — up to 12 microphones per bus and up to 144 microphones in total — are results from P2L2's own in-house testing, not a guaranteed or certified specification.
The IP is available to MIPI Alliance members. Talk to us about your channel count, target FPGA and integration requirements.
MIPI®, MIPI SoundWire® and SWI3S™ are trademarks or registered trademarks of MIPI Alliance, Inc. Used for descriptive purposes only; no affiliation, endorsement or certification is implied.