Interface
ULPI to an external PHY
A standard ULPI interface connects the core to an external USB 2.0 PHY, driven by the 60 MHz ULPI clock. Low-, Full- and High-Speed are all supported.
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USB 2.0 · ULPI Device Controller
Coming soon
USB 2.0 ULPI
USB 2.0 ULPI
High-Speed USB, straight into your AXI-Stream pipeline.
A USB 2.0 device controller with a ULPI interface to an external PHY. It supports Low-, Full- and High-Speed, and exposes every endpoint as an AXI-Stream — so payload moves through your processing pipeline without a round-trip over CPU RAM.
In development — details are preliminary and subject to change.
Up to 350 Mbit/sbulk IN, current measurements
LS / FS / HSLow-, Full- and High-Speed
AXI-Stream per EPno CPU-RAM round-trip
60 MHz ULPIexternal PHY, standard clock
The core in one sentence
A USB device that speaks AXI-Stream
The core connects to an external USB PHY over ULPI and presents each endpoint as an AXI-Stream. Payload flows directly between the endpoint and your processing pipeline, so there is no need to stage data in CPU RAM. EP0 (control) is handled by the CPU, with a TinyUSB-based stack planned.
Datapath
AXI-Stream per endpoint
Each endpoint exposes an AXI-Stream interface for easy integration into a processing pipeline — configurable per EP (FIFO size, packet splitter), with no round-trip over CPU RAM.
Control
EP0 on the CPU
The control endpoint (EP0) is handled by the CPU over AXI-Lite, with an interrupt line for events. A TinyUSB integration for the USB stack is planned.
Capabilities
What the core does
- USB 2.0 device controller with ULPI interface to an external PHY
- Supports Low-, Full- and High-Speed
- All transfer types — control, bulk, interrupt, isochronous — on all endpoints
- Up to 350 Mbit/s bulk IN transfer rate in current measurements
- Configurable endpoint interface: FIFO size, packet splitter
- Driven by the 60 MHz ULPI clock
Architecture
From PHY to processing pipeline
The USB Core sits between the external PHY (over ULPI) and your logic: a CPU configures it over AXI-Lite and receives interrupts, while endpoint data streams in and out over AXI-Stream — one stream per endpoint, in each direction.
Software & integration
Bring your own stack
RTOS & bare-metal via TinyUSB
For RTOS and bare-metal targets we propose a TinyUSB driver: TinyUSB is well established, ships drivers for many USB device classes and runs with or without an RTOS. A Linux implementation is currently in progress.
Streaming without the CPU
Because the endpoints are available directly as AXI-Stream, transfers do not have to pass through CPU RAM — data moves straight between USB and your fabric pipeline.
Status
Where the core stands
TodayIn development
Controller tested against individual transfer modes (control, bulk, interrupt, isochronous) without implementing a USB device class. Up to 350 Mbit/s bulk IN measured.
Software stackIn progress
A Linux implementation is currently in progress. For RTOS and bare-metal, a TinyUSB driver is planned — EP0 handled by the CPU, endpoint data over AXI-Stream.
Demo applicationPlanned
A USB camera is the intended demo project — a natural fit for the per-endpoint AXI-Stream datapath.
Interested in USB 2.0 on your FPGA?
This core is in development. Tell us your target FPGA, PHY and use case, and we will keep you posted and scope an early-access evaluation.
P2L2 GmbH