SPI Subnode IP (SPI Slave)

SPI Subnode, SPI Slave

The P2L2 SPI Slave IP Core is a highly configurable and efficient solution for establishing SPI communication between low-cost FPGAs and a microcontrollers, SoCs, or other FPGAs.

It features an advanced and patented synchronization scheme that allows for SPI clock frequencies to exceed the FPGA system clock rate, facilitating easier timing closure and resource efficiency.

The core supports configurable SPI clock phase and polarity, optional CRC16/CRC32 calculation for data integrity, and automated SPI frame/packet enumeration. Its streaming interfaces support both Intel/Altera Avalon and AXI, making it suitable for a wide range of applications where high SPI data rates are essential, even with low-cost FPGAs.

Typical applications are:

  • High data rates
  • Resource efficient connection of FPGA to a microcontroller or SoC
  • Allows even for low cost FPGA at high SPI data rates
  • Coupling of FPGA to FPGA
  • Coupling of FPGA to Microcontroller
 
 

Key Features

Configurable clock phase and polarity

f_SPI up to 1.66 * f_FPGA

CRC16 or CRC32 calculation

SPI Frame enumeration

AXI and AV-ST interface

Ultra low clock rate requirements

Supports all FPGAs of all vendors

Deeply verified and tested 

Download Datasheet

Exceptional Resource Usage and Timing

The following tables list the reachable frequencies and resource results for the maximum and minimum feature set of the P2L2 SPI Slave. 

Notes: 

  • The frequency fFPGA is the frequency of the clock domain inside the FPGA where the parallelized data from/to the SPI core is read/written.
  • The system frequency f_FPGA has to be at least 0.66 × f_SPI or higher according to the needs of the customer design.
  • Timing constraints that the connected SPI Main (e.g. a microcontroller) demands may decrease the maximum f_SPI from the values given in the table.
  • All Efinix results were reached with FPGAs of the C4 timing variant except the Trion T8F81 which is of the C2 timing variant.